module led_display_ctrl (
    input  wire               clk,
	input  wire               rst_n,
    input  wire [23:0]   cal_result,
 	output reg  [7:0] led_en,
	output reg        led_ca,
	output reg        led_cb,
    output reg        led_cc,
	output reg        led_cd,
	output reg        led_ce,
	output reg        led_cf,
	output reg        led_cg,
	output            led_dp 
);
	// wire rst_n = ~rst;

	reg [7:0]	    an =  8'b1111_1111;    // chip selection
	reg [7:0]      seg = 8'b1111_1111;    // segment selection
	
	// digit
	wire [3:0] h0;
	wire [3:0] h1; 
	wire [3:0] h2; 
	wire [3:0] h3; 
	wire [3:0] h4; 
	wire [3:0] h5;
	wire [3:0] h6; 
	wire [3:0] h7; 
	reg [4:0] hex_in; 

    // Separated digit of cal_result
	assign h0 = (cal_result & 32'h0000_000f) >> 6'd00;
	assign h1 = (cal_result & 32'h0000_00f0) >> 6'd04;
	assign h2 = (cal_result & 32'h0000_0f00) >> 6'd08;
	assign h3 = (cal_result & 32'h0000_f000) >> 6'd12;
	assign h4 = (cal_result & 32'h000f_0000) >> 6'd16;
	assign h5 = (cal_result & 32'h00f0_0000) >> 6'd20;
	assign h6 = (cal_result & 32'h0f00_0000) >> 6'd24;
	assign h7 = (cal_result & 32'hf000_0000) >> 6'd28;


	// counter
	reg  [31:0] cnt =     4'd0;
	wire [31:0] cnt_end = 32'd5_0000;


	// counter control
	always @(posedge clk or negedge rst_n) begin
		if(~rst_n || cnt == cnt_end)	              cnt <= 4'd0;
		else									cnt <= cnt + 4'd1;
	end

	// chip selection
	always @(posedge clk or negedge rst_n) begin
		if(~rst_n)	            an <= 8'b1000_0000;       // D0
        else if (cnt == 32'd0)  an[7:0] <= {an[0],an[7:1]};
		else 					an <= an;
	end

	// segement selection
	always @(posedge clk or negedge rst_n) begin
		if(~rst_n) begin
		      seg[6:0] <= 7'b111_1111;
		end
		else begin
			case(an)
				8'b0000_0001 : hex_in <= h0;     
				8'b0000_0010 : hex_in <= h1;      
				8'b0000_0100 : hex_in <= h2;  
				8'b0000_1000 : hex_in <= h3; 
				8'b0001_0000 : hex_in <= h4;  
				8'b0010_0000 : hex_in <= h5;  
				8'b0100_0000 : hex_in <= h6;  
				8'b1000_0000 : hex_in <= h7;  
				default      : hex_in <= 5'h16;  
			endcase

			case(hex_in)
				4'h0: seg[6:0] = 7'b0000001; 
				4'h1: seg[6:0] = 7'b1001111;
				4'h2: seg[6:0] = 7'b0010010;
				4'h3: seg[6:0] = 7'b0000110;
				4'h4: seg[6:0] = 7'b1001100;
				4'h5: seg[6:0] = 7'b0100100;
				4'h6: seg[6:0] = 7'b0100000;
				4'h7: seg[6:0] = 7'b0001111;
				4'h8: seg[6:0] = 7'b0000000;
				4'h9: seg[6:0] = 7'b0001100;
				4'ha: seg[6:0] = 7'b0001000;
				4'hb: seg[6:0] = 7'b1100000;
				4'hc: seg[6:0] = 7'b0110001;	
				4'hd: seg[6:0] = 7'b1000010;
				4'he: seg[6:0] = 7'b0110000;
				4'hf: seg[6:0] = 7'b0111000;
				default: seg[6:0] = seg[6:0];
			endcase
		end
	end
	
	//  leds control
    always @(posedge clk or negedge rst_n) begin
        if(~rst_n)	begin
			led_ca <= 1;
			led_cb <= 1;
			led_cc <= 1;
			led_cd <= 1;
			led_ce <= 1;
			led_cf <= 1;
			led_cg <= 1;
            led_en <=    ~an;  
		end
		else begin
            led_ca <= seg[6];
            led_cb <= seg[5];
            led_cc <= seg[4];
            led_cd <= seg[3];
            led_ce <= seg[2];
            led_cf <= seg[1];
            led_cg <= seg[0];
            led_en <=    ~an;  
        end
    end
	
	// decimal point control
	assign led_dp =   seg[7];

endmodule